Current front end of line (FEOL) defect density is incompatible with high yields in technologies such as 32 nanometer and below. A strong contributor of defects is the silicide module. Conventionally, full area silicidation is employed, which leads to a naturally high defect density due to the large silicide areas, e.g., nickel silicide (NiSi). A current silicidation process is schematically illustrated in FIGS. 1 through 4. FIGS. 1A (a top view) and 1B (a cross-sectional view) illustrate an FEOL device ready for silicidation with typical transistor gates 101 and spacers 103 on a silicon substrate 105. As illustrated in FIG. 2, nickel (Ni) 201 is deposited over the entire surface. After annealing and stripping unreacted Ni, large silicidated areas 301 are formed, as shown in FIGS. 3A (a top view) and 3B (a cross-sectional view). Typical problems and weaknesses of such an approach are encroachments and stringers, as illustrated in FIG. 4. When NiSi formation extends under the spacers (shown at 401) degradation or destruction of the transistor results. Also, gate-to-active area shorts (shown at 403) are generated by Ni residuals or platinum (Pt) particles. The probability of such defects is extremely high due to the large exposure area.
A need therefore exists for methodology enabling the fabrication of localized NiSi in semiconductors and the resulting devices exhibiting reduced defects.